FIG. 1 shows a simplified schematic diagram of an exemplary portion of a column stripe pattern for a memory array 100 of a NAND Flash memory device. It should be understood that the exemplary portion of memory array 100 shown in FIG. 1 is for illustrative purposes and should not be taken as limiting and that other NAND memory array embodiments according to the subject matter disclosed herein are possible and will be apparent to those skilled in the art with the benefit of the present disclosure.
In FIG. 1, a series of NAND memory strings 120 are arranged in memory array 100 and are coupled to bit lines BL0-BL5 and source lines SL (of which only one source line SL is shown). In each NAND memory string 120, a series of floating-gate, or floating-node, FET memory cells 102 are coupled together source-to-drain to form NAND memory string 120 (typically having 8, 16, 32, or more cells). Each floating gate/node FET memory cell 102 has a gate-insulator stack formed over a channel region. To further enable operation, each NAND memory string 120 of memory array 100 is formed in an isolation trench (not shown), thereby allowing the substrate of each isolation trench to be individually biased in a well-known manner for programming and erasure.
Word lines WL0-WL65 cross the NAND memory strings 120 and couple the control gates of memory cells 102 in adjacent memory strings 120 in order to enable, or select, a single memory cell 102 in each NAND memory string 120. In each NAND memory string 120, impurity doped regions (typically an N+ impurity) are formed between each gate insulator stack to form the source and drain regions of the adjacent memory cells 102, which additionally operate as connectors to couple the cells of the NAND string 120 together. In an exemplary alternative embodiment, the N+ doped regions are omitted and a single channel region is formed under a NAND memory string 120, thereby coupling the individual memory cells 102. Each NAND memory string 120 is coupled to select gates 104 that are formed at either end of each NAND memory string 120 and selectively couple opposite ends of each NAND memory string 120 to a bit line BL and to a source line SL. The select gates 104 are each coupled to gate select lines, i.e., select gate drain SDS and select gate source SGS, that control the coupling of NAND memory strings 120 to the bit lines BL and source lines SL, respectively, through select gates 104.
NAND memory array 100 is accessed in a well-known manner by a row decoder (not shown) that activates a row of memory cells by selecting a particular word select line WL that is coupled to the gates of the memory cell row. Word lines WL coupled to the gates of the unselected memory cells of each NAND memory string 120 are also driven. The unselected memory cells of each NAND memory string 120 are, however, typically driven by a higher gate voltage to operate them as pass transistors, thereby allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line SL to the column bit line BL through each floating gate/node memory cell of the series-coupled NAND memory string. The current that flows in the respective bits lines BL is restricted only by the stored data values of the row of selected memory cells. A column page of bit lines is selected and sensed, and then individual data words are selected from the sensed data words from the column page and communicated from the memory device.
In some exemplary embodiments, NAND memory array 100 is configured so that even numbered bit lines (i.e., BL0, BL2, BL4, etc.) are configured as part of an even column page, and odd numbered bit lines (i.e., BL1, BL3, etc.) are configured as part of an odd column page. In other exemplary embodiments, NAND memory array 100 is configured as an array without an even and odd column page arrangement.
The conventional programming technique for Flash/EEPROM memories program a bit or row (commonly referred to as a page) of a NAND memory array by applying a programming voltage or series of programming voltage pulses to the control gates of the selected memory cells and programming (or inhibiting) the selected memory cells to either program (set at logical “0” by the injection of charge to the floating gate or floating node of a memory cell) or inhibit (not program, usually intended to leave the cell erased and set at logical “1”) by coupling their channels to either a program or inhibit voltage.
In conventional programming operations in a NAND architecture Flash/EEPROM memory arrays, such as depicted by NAND memory array 100, a programming voltage is coupled to a word line WL that is coupled to the gate of the selected memory cell of a NAND memory string 120. The word lines WL coupled to the gates of the unselected memory cells of each NAND memory string 120 are also driven by a pass gate voltage Vpass in order to operate the unselected memory cells of the memory string 120 as pass transistors, and to generate a channel of carriers by capacitive coupling in the unselected memory cells so that the unselected memory cells pass current in a manner that is relatively unrestricted by their respectively stored data values. The NAND memory string 120 is then typically coupled to a bit line BL (or a source line SL) that has a program voltage placed upon it. The applied pass voltage Vpass also allows generation of a channel of carriers in the NAND memory string 120 and allows the memory cell that was selected for programming to couple through this channel of carriers to the bit line BL (or the source line SL), thereby applying a field that across the memory cell selected for programming that causes carriers to tunnel to the floating gate, or charge trapping layer, altering the threshold voltage level Vt of the selected memory cell and storing the data value. If a program-inhibit voltage is placed upon the coupled bit line BL or source line SL (also referred to as boosting), the applied field generated by the program-inhibit voltage is selected to be insufficient to tunnel carriers to the floating gate/node, and no data value is programmed and the memory cell remains in the erased state.
After programming the selected memory cell(s), a verify operation is then performed to confirm that the data was successfully programmed. If the programmed memory cell(s) of the erase block fail verification, the program and verify cycle is repeated until the data is successfully programmed or a selected number of iterations have passed and the programming operation is deemed to have failed.
It will be appreciated that for simplicity and/or clarity of illustration, elements depicted in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. The scaling of the figures does not represent precise dimensions and/or dimensional ratios of the various elements depicted herein. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.